VP531E View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

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VP531E

NTSC/PAL Digital Video Encoder

Zarlink Semiconductor Inc 

REGISTER DETAILS

BAR

RA7-0

Base register

Register address.

PART ID 2-0

ID17-00

Part number

Chip part identification (ID) number.

REV ID

REV7-0

Revision number

Chip revision ID number.

GCR

YCDELAY

Global Control

Luma to Chroma delay.

High = 37ns luma delay, this may be

used to compensate for group delay in

external filters.

Low = normal operation (default).

RAMPEN

Modulated ramp enable.

High = ramp output for differential phase

and gain measurements. A 27MHz clock

must be applied to PXCK pin.

Low = normal operation (default).

SL_HS_VS

1 = Slave to HS and VS inputs

VFS1-0

VOCR

CLAMPDIS

Video format select

VFS1 VFS0

00

01

10

11

NTSC (default)

PAL-B,D,G,H,I,N(Argentina)

Reserved

Reserved

Video Output Control

High = Clamp signal disable

Low = normal operation with clamp signal

enabled (default).

CHRBW

Chroma bandwidth select.

High = ±1·3MHz.

Low = ±650kHz (default)

SYNCDIS

High = Sync disable (in composite video

signal). COMPSYNC is not affected.

Low = normal operation with sync

enabled (default).

BURDIS

High = Chroma burst disable.

Low = normal operation, with burst

enabled (default).

LUMDIS

High = Luma input disable - force black

level with synchronisation pulses main-

tained.

Low = normal operation, with Luma input

enabled (default).

CHRDIS

High = Chroma input disable - force

monochrome.

Low = normal operation, with Chroma

input enabled (default).

VP531E/VP551E

PEDEN

High = Pedestal (set-up) enable a

7·5 IRE pedestal on lines 23-262 and

286-525. Valid for NTSC only

HANC

Horizontal Ancillary Data Control

DFI2-0(read only)Digital Field Identification, 000=Field1

ANCTREN

Ancillary timing reference enable. When

High use FIELD COUNT from ancillary

data stream. When low, data is ignored.

ANCID

AN7-1

AN0

Ancillary data ID

Ancillary data ID

Parity bit (odd)

Only ancillary data in REC 656 data

stream with the same ID as this byte will

be decoded by the VP531/VP551 to

produce H and V synchronisation and

FIELD COUNT.

SC_ADJ

SC7-0

Sub Carrier Adjust

Sub carrier frequency seed value, see

table 2.

FREQ2-0

FR17-00

Sub carrier frequency

24 bit Sub carrier frequency programmed

via I2C bus, see table 2. FREQ2 is the

most significant byte (MSB).

SCHPHM-L

SCH9-0

Sub carrier phase offset

9 bit Sub carrier phase relative to the

50% point of the leading edge of the

horizontal part of composite sync.

SCHPHM bit 0 is the MSB. The nominal

value is zero. This register is used to

compensate for delays external to the

VP531/VP551.

GPPCTL

CTL7-0

General purpose port control

Each bit controls port direction

Low = output High = input

GPPRD

RD7-0

General purpose port read data

I2C bus read from general purpose port

(only INPUTS defined in GPPCTL)

GPPWR

WR7-0

General purpose port write data

I2C bus write to general purpose port

(only OUTPUTS defined in GPPCTL)

HSOFFM-L

HSOFF9-0

SLAVE1

NCORSTD

VBITDIS

F_SWAP

SL_HS1-0

HCNT9-8

HS offset

This is a 10 bit number which allows the

user to offset the start of digital data input

with reference to the pulse HS.

H &V Slave mode control register

1 = NCO Line Reset Disable (NTSC only)

0 = Video blanked when Rec601 V bit set

1 = V bit is ignored

The odd and even fields are swapped

Selects pixel sample (1 to 4)

As HCNT7-0 but MSBs

7

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