ยตPD43257B
Write Cycle Timing Chart 2 (/CE1 Controlled)
Address (Input)
/CE1 (Input)
CE2 (Input)
/WE (Input)
tWC
tAS
tCW1
tCW2
tAW
tWP
tWR
I/O (Input)
High impedance
tDW
Data in
tDH
High
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
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2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
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Data Sheet M10693EJ7V0DS00