72605L20 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

View to exact match

72605L20

CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

Integrated Device Technology 

IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

ENA

(R/W A = 0)

PAEAB

CLKB

t CLKH

tCLKL

tCS

tCH

WRITE

n words in FIFO

tSKEW2 (1)

tPAE

ENA

(R/W B = 1)

n+1 words in FIFO

tPAE

(2)

tCS

tCH

READ

2704 drw 16

NOTES:

1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the

rising edge of CLKA and the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.

Figure 12. A→B Programmable Almost-Empty Flag Timing

CLKA

ENA

(R/W A = 0)

PAFAB

CLKB

tCLKH

tCLKL

(2)

t CS

tCH

WRITE

Full - (m+1) words in FIFO

tPAF

ENB

(R/W B = 1)

Full - m words in FIFO

tPAF

tCS

t CH

READ

2704 drw 17

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the

rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.

Figure 13. A→B Programmable Almost-Full Flag Timing

5.18

18

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