IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
tWC
W
D0ā8
t WPW
tDS
Figure 2. Write Operation
COMMERCIAL TEMPERATURE RANGES
tWR
tDH
2751 drw 05
SOCP
SOX
SO(1)
SO (2)
t SOCW
1/f SOCP
0
t SOX
t SOHZ
t SOLZ
t SOPD
1
t SOCW
nā1
Figure 3. Read Operation
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode.
2751 drw 06
SOCP
W
FF
LAST WRITE
IGNORED
WRITE
FIRST READ
0
1
nā1
ADDITIONAL
READS
0
1
nā1
FIRST WRITE
t WFF
t SOCFF
Figure 4. Full Flag from Last Write to First Read
2751 drw 07
5.34
6