CDP1882 View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

CDP1882

CMOS 6-Bit Latch and Decoder Memory Interfaces

Intersil 

CDP1881C, CDP1882, CDP1882C

TRUTH TABLE

INPUTS

OUTPUTS

(NOTE 1) (NOTE 1)

MWR

MRD

CE

CLK

MA4

MA5

CS0

CS1

CS2

CS3

1

1

X

X

X

X

1

1

1

1

X

X

1

X

X

X

1

1

1

1

0

X

0

1

0

0

0

1

1

1

0

X

0

1

1

0

1

0

1

1

0

X

0

1

0

1

1

1

0

1

0

X

0

1

1

1

1

1

1

0

0

X

0

0

X

X

Previous State

X

0

0

1

0

0

0

1

1

1

X

0

0

1

1

0

1

0

1

1

X

0

0

1

0

1

1

1

0

1

X

0

0

1

1

1

1

1

1

0

X

0

0

0

X

X

Previous State

NOTE:

1. CDP1881C Only

INPUTS

CE

CLK

X

1

X

1

X

0

Logic 1 = High, Logic 0 = Low, X = Don’t Care

MA0, MA1, MA2, MA3

1

0

X

OUTPUTS

A8, A9, A10, A11

1

0

Previous State

Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF,

(See Figure 1)

CDP1882

CDP1881C, CDP1882C

PARAMETER

VDD

(NOTE 1) (NOTE 2)

(NOTE 1) (NOTE 2)

(V)

MIN

TYP

MAX

MIN

TYP

MAX UNITS

Minimum Setup Time

Memory Address to CLOCK

tMACL

5

-

10

35

-

10

35

ns

10

-

8

25

-

-

-

ns

Minimum Hold Time

Memory Address After CLOCK

tCLMA

5

-

8

25

-

8

25

ns

10

-

8

25

-

-

-

ns

Minimum CLOCK Pulse Width

tCLCL

5

-

50

75

-

50

75

ns

10

-

25

40

-

-

-

ns

4-4

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