VV6501C001 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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VV6501C001

DUAL-MODE DIGITAL CAMERA CO-PROCESSOR

STMicroelectronics 

STV0681 Hardware Interfaces

STV0681

Figure 5: SDRAM Write Timing (16Mbit device, burst write)

DCLK

CKE

Command

A0-9,BA

A10

DQM

DQ

tCK

tL

tH

tCMS tCMH

ACTIVE

WRITE

ROW

ROW

tAS

tAH

tCMS

NOP

COLUMN

PRECHARGE

NOP

tDS

tDH

tCMH

DIN M

DIN M + 1

DIN M + 2

DIN M + 3

tRCD

tRC

tRAS

tRP

Symbol

tCK

tCH

tCL

tAC

tOH

tCMS

tCMH

tAS

Min.

166.45

½

½

0

82.88

82.85

82.88

Table 3: Timing parameters for SDRAM read/write

Max

166.89

½

Units

ns

tCK

tCK

tCK

ns

ns

ns

ns

Symbol

tDS

tDH

tRCD

tRAS

tRC

tRP

tRCD

tAH

Min.

81.01

83.41

1

5

7

2

1

82.76

Max

5

Units

ns

ns

tCK

tCK

tCK

tCK

tCK

ns

4.2.3

SDRAM refresh period

The SDRAM refresh period from STV0681 is guaranteed to be inferior or equal to 15.6µs during

‘Snapshot’/self-timer/continuous/tethered video modes of operation (that is not standby mode). In

standby mode, the SDRAM is set to self-refresh, therefore no refresh from STV0681 takes place.

4.2.4 SDRAM initialisation period

The SDRAM initialisation period is currently set to 981µs in STV0681.

20/44

ADCS 7283313C

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