SST89E52RD-33-C-NI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
View to exact match
SST89E52RD-33-C-NI Datasheet PDF : 81 Pages
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FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
SuperFlash Configuration Register (SFCF)
Location
7
6
5
4
3
2
1
B1H
-
IAPEN
-
-
-
-
SWR
Data Sheet
0
BSEL
Reset Value
x0xxxx00b
Symbol
IAPEN
SWR
BSEL
Function
Enable IAP operation
0: IAP commands are disabled
1: IAP commands are enabled
Software Reset
See Section 10.2, “Software Reset”
Program memory block switching bit
See Figures 3-1 through 3-3 and Table 3-2
SuperFlash Command Register (SFCM)
Location
7
6
5
B2H
FIE
FCM6
FCM5
4
FCM4
3
FCM3
2
FCM2
1
FCM1
0
FCM0
Reset Value
00H
Symbol
FIE
FCM[6:0]
Function
Flash Interrupt Enable.
0: INT1# is not reassigned.
1: INT1# is re-assigned to signal IAP operation completion.
External INT1# interrupts are ignored.
Flash operation command
000_0001b Chip-Erase
000_1011b Sector-Erase
000_1101b Block-Erase
000_1100b Byte-Verify1
000_1110b Byte-Program
000_1111b Prog-SB1
000_0011b Prog-SB2
000_0101b Prog-SB3
000_1001b Prog-SC0
000_1001b Prog-SC1
000_1000bEnable-Clock-Double
All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
SuperFlash Address Registers (SFAL)
Location
7
B3H
6
5
4
3
2
1
SuperFlash Low Order Byte Address Register
0
Reset Value
00H
Symbol
SFAL
Function
Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Registers (SFAH)
Location
7
B4H
6
5
4
3
2
1
SuperFlash High Order Byte Address Register
0
Reset Value
00H
Symbol
SFAH
Function
Mailbox register for interfacing with flash memory block. (High order address register).
©2006 Silicon Storage Technology, Inc.
21
S71255-05-000
5/06
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