8906 View Datasheet(PDF) - Allegro MicroSystems
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Description
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8906
Allegro MicroSystems
8906 Datasheet PDF : 12 Pages
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8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FAULT
BRAKE
V FAULT – V D
BRAKE
ACTIVATED
CB
RB
t BRK
VBRK
Dwg. OP-004
Braking. A dynamic braking feature of the A8906CLB shorts the
three motor windings to ground. This is accomplished by turning the
three source drivers OFF and the three sink drivers ON. Activation of
the brake can be implemented through the BRAKE input. The supply
voltage for the brake circuitry is the CRES voltage, allowing the brake
function to remain active after power failure. Power-down braking with
delay can be implemented by using an external RC and other compo-
nents to control the brake terminal, as shown. Brake delay can be set
using the equation below. Once the brake is activated, due to the
inherent capacitive input, the three sink
drivers will remain active until the device is
reset.
tBRK = RBCB
1 – ln
VBRK
VFAULT - VD
Centertap. The A8906CLB internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.
External Component Selection. Appli-
cations information regarding the selection of
external component values is available from
the factory for external component selection,
frequency-locked loop speed control, and
commutation delay capacitor selection.
BYPASS
VRET
FAULT
RB
TYPICAL APPLICATION
V
BB
1
VBB
COMMUTATION
DELAY
24
2
23
C D2
3
22
CWD
4
21
C ST
5
20
6
19
7
18
8
MUX
17
99
10
CB
11
12
CRES
0.22 µF
FLL
16
BOOST
CHARGE
PUMP
VDD 15
14
13
CD1
DATA IN
CLOCK
CHIP SELECT
RESET
BYPASS
DATA OUT
OSC (REF)
+5 V
R F1
CF1
SECTOR
DATA
CF2
Dwg. EP-036C
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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