MC14LC5540DW View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

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MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

Level

+ Full Scale

+ Zero

– Zero

– Full Scale

Sign Bit

1

1

0

0

Table 1. PCM Full Scale and Zero Words

Mu–Law

Chord Bits

Step Bits

Sign Bit

000

0000

1

111

1111

1

111

1111

0

000

0000

0

A–Law

Chord Bits

010

101

101

010

Step Bits

1010

0101

0101

1010

The length of the FST enable tells the DSP what encoding

algorithm to use. The transmit logic decides on each frame

sync whether it should interpret the next frame sync pulse as

a Long or a Short Frame Sync. The device is designed to

prevent PCM bus contention by not allowing the PCM data

output to go low impedance for at least two frame sync

cycles after power is applied or when coming out of the

power–down mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit PCM data word. Thus the

PCM digital switch only needs to be able to generate one

type of frame sync for use by both transmit or receive sec-

tions of the device.

The logical AND of the receive frame sync with the receive

data clock tells the device to start latching the serial word into

the receive data input on the falling edges of the receive data

clock. The internal receive logic counts the receive data

clock falling edges while the FSR enable is high and trans-

fers the enable length and the PCM data word into internal

registers for access by the DSP machine which also sets the

DSP’s decoder interrupt.

The receive digital section of this device accepts serial

ADPCM (PCM) words at the DR pin under the control of the

BCLKR and FSR pins. The FSR enable duration measured

in BCLKR cycles, tells the device which decode algorithm

(i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM)

the DSP machine should use for the word that is being re-

ceived at the DR pin. This algorithm may be changed on a

frame by frame basis.

When the device is programmed to be in the PCM Codec

mode by BR0 (4:3), the device will output and input the com-

plete 8–bit PCM words using the Long Frame Sync clocking

format as though the FST and FSR pulses were held high for

8 data clock cycles.

The DSP machine receives an interrupt when an ADPCM

word has been received and is waiting to be decoded into a

PCM word. The DSP machine performs a decode and an en-

code every frame when the device is operating in its full–

duplex conversation mode. The DSP machine decodes the

ADPCM word according to CCITT G.726 for 32 kbps,

24 kbps, and 16 kbps.

Short Frame Sync

Short Frame Sync is the industry name for this type of

clocking format which controls the transfer of the ADPCM

data words (see Figure 5). This device uses Short Frame

Sync timing for 32 kbps ADPCM only. The “Frame Sync” or

“Enable” is used for two specific synchronizing functions.

The first is to synchronize the ADPCM data word transfer,

and the second is to control the internal analog to digital and

digital to analog conversions. The term “Sync” refers to the

function of synchronizing the ADPCM data word onto or off of

the multiplexed serial ADPCM data bus, also known as a

PCM highway. The term “Short” comes from the duration of

the frame sync measured in PCM data clock cycles. Short

Frame Sync timing occurs when the frame sync is used as a

“pre–synchronization” pulse that is used to tell the internal

logic to clock out the ADPCM data word under complete con-

trol of the data clock. The Short Frame Sync is held high for

one falling data clock edge. The device outputs the ADPCM

data word beginning with the following rising edge of the data

clock. This results in the ADPCM output going low imped-

ance with the rising edge of the transmit data clock, and re-

maining low impedance until the middle of the LSB (three

and a half PCM data clock cycles).

The device recognizes Short Frame Sync clocking when

the frame sync is held high for one and only one falling edge

of the transmit data clock. The transmit logic decides on each

frame sync whether it should interpret the next frame sync

pulse as a Long or a Short Frame Sync. It is not recom-

mended to switch between Long Frame Sync and Short

Frame Sync clocking without going through a power–down

cycle due to bus contention problems. The device is de-

signed to prevent PCM bus contention by not allowing the

ADPCM data output to go low impedance for at least two

frame sync cycles after power is applied or when coming out

of a powered down mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit ADPCM data word. Thus the

PCM digital switch only needs to be able to generate one

type of frame sync for use by both transmit or receive sec-

tions of the device.

The falling edge of the receive data clock (BCLKR) latch-

ing a high logic level at the receive frame sync (FSR) input

tells the device to start latching the 4–bit ADPCM serial word

into the receive data input on the following four falling edges

of the receive data clock. The internal receive logic counts

the receive data clock cycles and transfers the ADPCM data

word to a register for access by the DSP.

When the device is programmed to be in the PCM Codec

mode by BR0 (4:3), the device will output the complete 8–bit

PCM word using the Short Frame Sync clocking format. The

8–bit PCM word will be clocked out (or in) the same way that

the 4–bit ADPCM word would be, except that the fourth bit

will be valid for the full BCLKT period and the eighth bit will be

valid for only one half of the BCLKT period.

MC14LC5540

14

MOTOROLA

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