SAKC505A-2R View Datasheet(PDF) - Infineon Technologies

Part Name

Description

View to exact match

SAKC505A-2R

8-Bit Single-Chip Microcontroller

Infineon Technologies 

C505/C505C/C505A/C505CA

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name

Address Contents after

Reset

CAN

Controller

(C505C/

C505CA

only)

CR

SR

IR

BTR0

BTR1

GMS0

GMS1

UGML0

UGML1

LGML0

LGML1

UMLM0

UMLM1

LMLM0

LMLM1

Control Register

Status Register

Interrupt Register

Bit Timing Register Low

Bit Timing Register High

Global Mask Short Register Low

Global Mask Short Register High

Upper Global Mask Long Register Low

Upper Global Mask Long Register High

Lower Global Mask Long Register Low

Lower Global Mask Long Register High

Upper Mask of Last Message Register Low

Upper Mask of Last Message Register High

Lower Mask of Last Message Register Low

Lower Mask of Last Message Register High

Message Object Registers :

F700H

F701H

F702H

F704H

F705H

F706H

F707H

F708H

F709H

F70AH

F70BH

F70CH

F70DH

F70EH

F70FH

01H

XXH 3)

XXH 3)

UUH 3)

0UUUUUUUB 3)

UUH 3)

UUU11111B 3)

UUH 3)

UUH 3)

UUH 3)

UUUUU000B 3)

UUH 3)

UUH 3)

UUH 3)

UUUUU000B 3)

MCR0

MCR1

UAR0

UAR1

LAR0

LAR1

MCFG

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

Message Control Register Low

Message Control Register High

Upper Arbitration Register Low

Upper Arbitration Register High

Lower Arbitration Register Low

Lower Arbitration Register High

Message Configuration Register

Message Data Byte 0

Message Data Byte 1

Message Data Byte 2

Message Data Byte 3

Message Data Byte 4

Message Data Byte 5

Message Data Byte 6

Message Data Byte 7

F7n0H 5)

F7n1H 5)

F7n2H 5)

F7n3H 5)

F7n4H 5)

F7n5H 5)

F7n6H 5)

F7n7H 5)

F7n8H 5)

F7n9H 5)

F7nAH 5)

F7nBH 5)

F7nCH 5)

F7nDH 5)

F7nEH 5)

UUH 3)

UUH 3)

UUH 3)

UUH 3)

UUH 3)

UUUUU000B 3)

UUUUUU00B3)

XXH 3)

XXH 3)

XXH 3)

XXH 3)

XXH 3)

XXH 3)

XXH 3)

XXH 3)

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by

a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5) The notation “n“ (n= 1 to F) in the message object address definition defines the number of the related

message object.

Data Sheet

21

12.00

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