SAA4956TJ View Datasheet(PDF) - Philips Electronics

Part Name

Description

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SAA4956TJ

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

5 BLOCK DIAGRAM

handbook, full pageDw0id(tVh0) to D11(Y7) IE

12

NREN SCL SDA

14 to 3 18

40 1

20

WE RSTW SWCK

17 16 15

DATA INPUT AND

WRITE MASK

BUFFER (×13)

I2C-BUS

INTERFACE

12 + 1

I2C-bus control

D0 internal

IE internal

IE

internal

SAA4956TJ

INPUT BUFFER 3

(×3)

SERIAL WRITE/READ2 CONTROLLER

NOISE

REDUCTION

12 + 1

DATA

MUX

12 D-field delay

DATA MUX

12

12

12 + 1

mini cache write/read2 control + cache transfer

SERIAL WRITE REGISTER

20-WORD (×13)

20 × (12 + 1)

PARALLEL WRITE REGISTER

20-WORD (×13)

20 × (12 + 1)

read2

control

WRITE REGISTER

MINI CACHE

12-WORD (×12)

READ2

READ

REGISTER REGISTER

MEMORY ARRAY

245760-WORD (×12)

write

control

load write

block

address

read2

acknowledge

write

acknowledge

D0

internal

IE

internal

WRITE ADDRESS

COUNTER

MEMORY

ARBITRATION

LOGIC

READ2 ADDRESS

COUNTER

REFRESH ADDRESS

COUNTER

READ ADDRESS

COUNTER

+3.3 V

VDD 19

VDD(P) 21

VDD(O) 22

100 nF

GND 2

OGND 39

20 × 12

PARALLEL READ2 REGISTER

20-WORD (×12)

20 × 12

SERIAL READ2 REGISTER

20-WORD (×12)

20 × 12

PARALLEL READ REGISTER

20-WORD (×12)

20 × 12

SERIAL READ REGISTER

20-WORD (×12)

OE

internal

refresh

clock

CLOCK

OSCILLATOR

12

12

DATA MUX

DATA OUTPUT

BUFFER (×12)

27 to 38

12

Q0(V0) to Q11(Y7)

mini cache read control

OE

internal

INPUT BUFFER

3

(×4)

23 24 25 26

OE RE RSTR SRCK

read

control

read

acknowledge

load read

block

address

SERIAL READ CONTROLLER

MGR687

Pin 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.0 V

instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.

Fig.1 Block diagram.

1998 Dec 08

5

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