74ACT280 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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74ACT280

9 BIT PARITY GENERATOR/CHECKER

STMicroelectronics 

74ACT280

9 BIT PARITY GENERATOR/CHECKER

s HIGH SPEED: tPD = 7ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS

VIH = 2V (MIN.), VIL = 0.8V (MAX.)

s 50Ω TRANSMISSION LINE DRIVING

CAPABILITY

DIP

SOP

TSSOP

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

s BALANCED PROPAGATION DELAYS:

t(s) tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

c VCC (OPR) = 4.5V to 5.5V

u s PIN AND FUNCTION COMPATIBLE WITH

rod 74 SERIES 280

s IMPROVED LATCH-UP IMMUNITY

te P DESCRIPTION

le The 74ACT280 is an advanced high-speed CMOS

o 9 BIT PARITY GENERATOR CHECKER

s fabricated with sub-micron silicon gate and

b double-layer metal wiring C2MOS tecnology.

O It is composed of nine data inputs (A to I) and odd/

- even parity outputs (ΣODD and ΣEVEN). The nine

) data inputs control the output conditions. When

t(s the number of high level input is odd, ΣODD

c output is kept high and ΣEVEN output low.

ORDER CODES

PACKAGE

DIP

SOP

TSSOP

TUBE

74ACT280B

74ACT280M

T&R

74ACT280MTR

74ACT280TTR

Conservely, when the output is even, ΣEVEN

output is kept high and ΣODD low.

The IC generates either odd or even parity making

it flexible application. The word-length capability is

easly expanded by cascading.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Obsolete Produ PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

1/9

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