CY7C185-35SC(2001) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

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CY7C185-35SC
(Rev.:2001)

8K x 8 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

rite Cycle No. 2 (CE Controlled)[12,13,14]

ADDRESS

CE1

tSA

CE2

WE

DATA I/O

tWC

tSCE1

tSCE2

tAW

tHA

tSD

tHD

DATA IN VALID

Write Cycle No. 3 (WE Controlled, OE LOW)[12,13,14,15]

tWC

ADDRESS

CE1

tSCE1

CE2

tSCE2

tAW

tHA

tSA

WE

DATA I/O

NOTE 13

tHZWE

tSD

DATA IN VALID

tHD

tLZWE

Notes:

14. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

CY7C185

C185–9

C185–10

Document #: 38-05043 Rev. **

Page 6 of 11

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