PI6C100 View Datasheet(PDF) - Pericom Semiconductor
Part Name
Description
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PI6C100 Datasheet PDF : 13 Pages
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PI6C100
Precision Clock Synthesizer
for Desktop PCs 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Minimum and Maximum Expected Capacitive Loads
Clock
Min. Load Max. Load Units
Notes
CPU Clocks (HCLK)
10
20
1 device load, possible 2 loads
PCI Clocks (PCLK)
30
30
Meets PCI 2.1 requirements
48 MHz Clock
10
20
pF 1 device load
REF
10
20
1 device load
APIC
10
20
2 device loads
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500W resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for
CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still
within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
21$+
CPUCLK
33Ω
4
PCICLK
33Ω
8
REF
22Ω/33Ω
3
APIC
33Ω
2
48MHZ
2
22Ω
CL
CL
CL
CL
CL
1 Device load
Meets PCI2.1 Req.
1 Device load
2 Device loads
1 Device load
208
PS8142A 10/13/98
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