Philips Semiconductors
1-port 400 Mbps physical layer interface
Product data
PDI1394P25BY
17.1 External Component Connections
REFER TO SECTION 17.5
12 pF
12 pF
24.576 MHz
VDD
0.1 µF
0.001 µF
CONNECT RESET TO THE SAME SOURCE AS
THE LINK IC OR THROUGH OPTOCOUPLER FOR
GALVANIC ISOLATION. USE 0.1 µF CAPACITOR
TO GND ONLY IN NON-LINK DESIGNS.
POWER DOWN
1 SYSCLK
2 CTL0
3 CTL1
4 D0
5 D1
6 D2
7 D3
8 D4
9 D5
10 D6
11 D7
12 PD
LINK PULSE OR
LINK VDD OR VDD
(REFER TO
FIGURES 7 AND 8)
PDI1394P25BY
AGND 36
AV DD 35
R1 34
R0 33
AGND 32
TPBIAS 31
TPA0+ 30
TPA0– 29
TPB0+ 28
TPB0– 27
AGND 26
AV DD 25
6.34 kΩ ±1%
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE CONNECTION
(REFER TO FIGURES 4 AND 5)
390 kΩ
See Figure 6 for recommended power and ground connections.
Figure 10. External Component Connections
SV001922
2002 Oct 11
20