MT9M001 View Datasheet(PDF) - Micron Technology
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MT9M001 Datasheet PDF : 32 Pages
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MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Figure 5: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Output Data Timing
The data output of the MT9M001 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 6: Timing Example of Pixel Data
LINE_VALID
PIXCLK
DOUT9-DOUT0
Blanking
(9P:00)
(9P:10)
....
....
Valid Image Data
....
P2
(9:0)
(9P:30) (9P:40) . . . .
P(9n:0-1)
Blanking
(9P:n0)
The rising edges of the PIXCLK signal are nominally timed to occur on the rising DOUT
edges. This allows PIXCLK to be used as a clock to latch the data. DOUT data is valid on
the falling edge of PIXCLK. The PIXCLK is HIGH while master clock is HIGH and then
LOW while master clock is LOW. It is continuously enabled, even during the blanking
period. The parameters P1, A P2, and Q in Figure 7 are defined in Table 3.
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals
FRAME_VALID
LINE_VALID
Number of master clocks P1 A
Q
...
...
...
A
Q
A
P2
80a3e031
MT9M001_DS_2.fm - Rev.C 7/05 EN
8
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©2004 Micron Technology, Inc. All rights reserved.
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