MSM7581 View Datasheet(PDF) - Oki Electric Industry

Part Name

Description

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MSM7581

ITU-T G.721 4ch ADPCM TRANSCODER

Oki Electric Industry 

¡ Semiconductor

MSM7581

THR Processing Timing

Timing Block Diagrams, when CODER and DECODER output data, are shown in the following

figures.

The parallel to serial conversion of the output unit employs a load format and the load point is

at the rising edge of a synchronous signal.

Therefore, input THR signal with respect to SYXA for CODER with timing of satisfying ts and

th conditions shown in the figure.

For DECODER, THR signal should be input even of through-data is input.

The input timing should satisfy the conditions shown in the following figures.

CODER

SYXP

SIP

BCKP

THR

Serial 8

Parallel

Latch

Latch timing=A

PCM side SYNC (SYXP)

PCM Input (SIP)

MSB

Internal Latch timing (A)

Internal Input Data

Through-data

8b

ADPCM

CODER

S

E

L

4b

Parallel

Serial

LSB

Through-data

SYNCA

SOA

BCLKA

ADPCM side SYNC (SYXA)

Through-data Output (SOA)

MSB

BCKA

THR

ts

th

ts=100ns or more

th=100ns or more

Note: That data-ship may occur when the rising edge (data load point) of SYXA and input of

the internal latch timing overlap each other.

12/18

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