MK2049-02 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
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MK2049-02 Datasheet PDF : 12 Pages
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MK2049-02/03
Communications Clock PLLs
MK2049-02 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0000
0001
0010
0011
0100
0101
0110
0111
1100
1101
CLK1
(Note 3)
1.544
2.048
22.368
17.184
19.44
16.384
24.576
25.92
10.24
4.096
CLK2 Crystal
3.088
4.096
44.736
34.368
38.88
32.768
49.152
51.84
20.48
8.192
12.352
12.288
11.184
11.456
12.96
8.192
12.288
12.96
10.24
12.288
CLK3
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
MK2049-02 Output Decoding Table – Loop Timing Mode (MHz)
ICLK
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
1000
1001
1010
1011
CLK1
(Note 3)
1.544
2.048
22.368
17.184
CLK2 Crystal
3.088
4.096
44.736
34.368
12.352
12.288
11.184
11.456
CLK3
N/A
N/A
N/A
N/A
MK2049-02 Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 28
10 - 14
FS3 FS2 FS1 FS0
1110
1111
CLK1
(Note 3)
ICLK/2
2*ICLK
CLK2 Crystal
ICLK ICLK/2
4*ICLK ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
CLK3
N/A
N/A
= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.
Note 3: CLK1 rising or falling edge may align with the input clock. See Figure 1 on page 6
for more details.
MDS 2049-02/03 B
4
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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