MC145540 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

View to exact match

MC145540

ADPCM Codec

Motorola => Freescale 

power amplifier outputs. Connecting PI to VDD will power down these amplifiers and the PO + and PO –

outputs will be high impedance.

PO –

Power Amplifier Output (Inverting) (Pin 11)

This is the inverting power amplifier output that is used to provide a feedback signal to the PI pin to set

the gain of the push-pull power amplifier outputs. This power amplifier is powered from VEXT and its

output can swing to within 0.5 V of VSS and VEXT. This should be noted when setting the gain of this

amplifier. This pin is capable of driving a 300 Ω load to PO + independent of supply voltage. The PO +

and PO – outputs are differential (push-pull) and capable of driving a 300 Ω load to 3.15 V peak, which is

6.3 V peak-to-peak when a nominal 5 V power supply is used for VEXT. The bias voltage and signal

reference for this pin may be dc referenced to either the VAG pin or a voltage of half of VEXT by BR2 (b7).

Low impedance loads must be between PO + and PO –. This pin is high impedance when the device is in

the analog power-down mode. This pin is high impedance except when it is enabled for analog signal

output.

PO +

Power Amplifier Output (Non-Inverting) (Pin 12)

This is the non-inverting power amplifier output that is an inverted version of the signal at PO –. This

power amplifier is powered from VEXT and its output can swing to within 0.5 V of VSS and VEXT. This pin

is capable of driving a 300 Ω load to PO –. This pin may be dc referenced to either the VAG pin or a

voltage of half of VEXT by BR2 (b7). This pin is high impedance when the device is in the analog power-

down mode. This pin is high impedance except when it is enabled for analog signal output. See PI and

PO– for more information.

2.4.3 ADPCM/PCM Serial Interface

FST

Frame Sync, Transmit (Pin 18)

When used in the Long Frame Sync or Short Frame Sync mode, this pin accepts an 8 kHz clock that

synchronizes the output of the serial ADPCM data at the DT pin.

BCLKT

Bit Clock, Transmit (Pin 19)

When used in the Long Frame Sync or Short Frame Sync mode, this pin accepts any bit clock frequency

from 64 to 5120 kHz.

DT

Data, Transmit (Pin 20)

This pin is controlled by FST and BCLKT and is high-impedance except when outputting data.

SPC

Signal Processor Clock (Pin 21)

This input accepts a clock frequency from 20.48 to 23.04 MHz that is used as the DSP engine master

clock. Internally the device divides down this clock to generate the 256 kHz clock required by the PCM

Codec. See Section 2.2.6 for additional information. (This clock may be optionally specified for higher

frequencies. Contact the factory for more information.)

DR

Data, Receive (Pin 25)

ADPCM data to be decoded are applied to this input, which operates synchronously with FSR and

BCLKR to enter the data in a serial format.

MOTOROLA

MC145540

2-13

Share Link: