MC06XSD200FK View Datasheet(PDF) - Freescale Semiconductor

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MC06XSD200FK

Dual 6.0 mOhm High Side Switch

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Unless specified otherwise: 8.0 V  VPWR  36 V, 3.0 V  VDD  5.5 V, -40 C  TA  125 C, GND = 0 V. Typical values are

average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Parameter

Symbol

Min

Typ

Max

Unit

SPI INTERFACE ELECTRICAL CHARACTERISTICS(41)

Maximum Operating Frequency of the Serial Peripheral Interface (SPI)(42)

Required Low-state Duration for reset RSTB(43)

f SPI

–

–

8.0

MHz

t WRSTB

10

–

–

s

Required duration from the Rising to the Falling Edge of CSB (Required Setup

Time)(44)

t CSB

1.0

–

–

s

Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)(44)

t ENBL

5.0

–

Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(44)

t LEAD

500

–

Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)(44)

t LAG

60

–

Required High State Duration of SCLK (Required Setup Time)(44)

t WSCLKh

50

–

Required Low State Duration of SCLK (Required Setup Time)(44)

t WSCLKl

50

–

SI to Falling Edge of SCLK (Required Setup Time)(45)

t SI (SU)

15

–

Falling Edge of SCLK to SI (Required hold Time of the SI signal)(45)

t SI (H)

30

–

SO Rise Time

CL = 80 pF

t RSO

–

–

–

s

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

20

ns

SO Fall Time

CL = 80 pF

t FSO

–

–

20

ns

SI, CSB, SCLK, Max. Rise Time allowing operation at fSPI = 8.0 MHz(45)

t RSI

–

–

11

ns

SI, CSB, SCLK, Max. Fall Time allowing operation at fSPI = 8.0 MHz(45)

t FSI

–

–

11

ns

Time from Rising Edge of SCLK to reach a valid level at the SO pin(46)

tVALID

–

–

44

ns

Time from Falling Edge of CSB to reach low-impedance on SO (access time)(47)

t SOEN

–

–

30

ns

Time from Rising Edge of CSB to reach high-impedance on SO pin (turn off time) tSODIS

30

ns

Notes:

41. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k

42. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V)

ceramic speed-up capacitors in parallel with the >8.0 k input resistors are required on pins SCLK, SI, SO, CS

43. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs

inactive).

44. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state.

45. Rise and Fall time of incoming SI, CSB, and SCLK signals.

46. Time required for output data to be available for use at SO, measured with a 80 pF capacitive load.

47. Time required for output data to be terminated at SO measured without a series resistorconnected CSB.

Analog Integrated Circuit Device Data

Freescale Semiconductor

06XSD200

19

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