A62S7332E-5 View Datasheet(PDF) - AMIC Technology

Part Name

Description

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A62S7332E-5

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

AMIC Technology 

A63G7332 Series

Timing Waveforms

CLK

ADSP

ADSC

ADDRESS

GW,BWE

BW1-BW4

CE

(NOTE *2)

ADV

tKC

tKH

tKL

tADSS

tADSH

tAS

tAH

A1

tWS

tADSS

tADSH

A2

tWH

tCES

tCEH

tADVS

OE

DOUT

(NOTE *3)

tKQLZ

High-Z

tOEHZ

Q(A1)

tKQ

Single READ

tADVH

ADV suspends

burst

tOEQ

tOELZ

tKQ

tKQX

Q(A2)

Q(A2+1)

(NOTE *1)

Q(A2+2)

BURST READ

Q(A2+3)

A3

Burst continued with

new base address

Delselected

cycle

(NOTE *4)

Q(A2)

Q(A2+1)

Burst wraps around

to its initial state

tKQHZ

Q(A3)

Read Timing

Notes:

*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately

following A2.

*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to

be driven until after the rising edge of the following clock.

PRELIMINARY (December, 1998, Version 2.1)

11

AMIC Technology, Inc.

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