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AT27LV520-70 View Datasheet(PDF) - Atmel Corporation

Part Name
Description
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AT27LV520-70 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Features
8-bit Multiplexed Addresses/Outputs
Fast Read Access Time – 70 ns
Dual Voltage Range Operation
– Low-voltage Power Supply Range, 3.0V to 3.6V, or
– Standard 5V ± 10% Supply Range
Pin Compatible with Standard AT27C520
Low-power CMOS Operation
– 20 µA max. Standby for ALE = VIH and VCC = 3.6V
– 29 mW max. Active at 5 MHz for VCC = 3.6V
JEDEC Standard Packages
– 20-lead TSSOP
– 20-lead SOIC
High-reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
RapidProgramming Algorithm – 50 µs/Byte (Typical)
CMOS- and TTL-compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Range
Description
The AT27LV520 is a low-power, high-performance, 524,288-bit one-time programma-
ble read-only memory (OTP EPROM) organized 64K by eight bits. It incorporates
latches for the eight lower order address bits to multiplex with the eight data bits. This
minimizes system chip count, reduces cost, and simplifies the design of multiplexed
bus systems. It requires only one power supply in the range of 3.0V to 3.6V for normal
read mode operation, making it ideal for fast, portable systems using battery power.
Any byte can be accessed in less than 70 ns.
The AT27LV520 is available in 173 mil, 20-lead TSSOP and 300 mil, 20-lead SOIC,
one-time programmable (OTP) plastic packages.
(continued)
Pin Configurations
Pin Name
A8 - A15
AD0 - AD7
OE /VPP
ALE
Function
Addresses
Addresses/Outputs
Output Enable/Program Supply
Address Latch Enable
512K (64K x 8)
Multiplexed
Addresses/
Outputs
Low-voltage
OTP EPROM
AT27LV520
TSSOP Top View
A10 1
A12 2
A14 3
ALE 4
VCC 5
OE/VPP 6
A15 7
A13 8
A11 9
A9 10
20 A8
19 AD1
18 AD3
17 AD5
16 AD7
15 GND
14 AD6
13 AD4
12 AD2
11 AD0
SOIC Top View
OE/VPP 1
A15 2
A13 3
A11 4
A9 5
AD0 6
AD2 7
AD4 8
AD6 9
GND 10
20 VCC
19 ALE
18 A14
17 A12
16 A10
15 A8
14 AD1
13 AD3
12 AD5
11 AD7
Rev. 0911D–05/00
1

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