AD8345-EVAL(REV0) View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD8345-EVAL Datasheet PDF : 16 Pages
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AD8345–SPECIFICATIONS (VS = 5 V; LO= –2 dBm @ 800 MHz, 50 ⍀ source and load impedances, I and Q inputs
0.7 V ؎ 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency.
TA = 25؇C, unless otherwise noted.)
Parameters
Conditions
Min
Typ
Max Unit
RF OUTPUT
Operating Frequency1
Output Power
Output P1 dB
Noise Floor
Quadrature Error
I/Q Amplitude Balance
LO Leakage
Sideband Rejection
Third Order Distortion
Second Order Distortion
Equivalent Output IP3
Equivalent Output IP2
Output Return Loss (S22)
250
–3
20 MHz Offset from LO, All BB
Inputs at 0.7 V
(CDMA IS95 Setup, Refer to Figure 13)
(CDMA IS95 Setup, Refer to Figure 13)
–1
2.5
–155
0.5
0.2
–42
–42
–52
–60
25
59
–20
1000
+2
MHz
dBm
dBm
dBm/Hz
Degree rms
dB
–33 dBm
–34 dBc
dBc
dBc
dBm
dBm
dB
RESPONSE TO CDMA IS95
BASEBAND SIGNALS
ACPR
EVM
Rho
(Refer to Figure 13)
–72
dBc
1.3
%
0.9995
LO INPUT
LO Drive level
LOIP Input Return Loss (S11)2
–10
–2
No Termination on LOIP, LOIN at
–5
AC Ground
50 Ω Terminating Resistor, Differential
–9
Drive via Balun
0
dBm
dB
dB
BASEBAND INPUTS
Input Bias Current
Input Capacitance
DC Common Level
Bandwidth (3 dB)
10
2
0.6
0.7
Full Power (0.7 V ± 0.3 V on Each
80
Input, Refer to TPC 2)
µA
pF
0.8 V
MHz
ENABLE
Turn-On
Turn-Off
ENBL High Threshold (Logic 1)
ENBL Low Threshold (Logic 0)
Enable High to Output within 0.5 dB of
Final Value
Enable Low to Supply Current Dropping
below 2 mA
POWER SUPPLIES
Voltage
2.7
Current Active
50
Current Standby
2.5
1.5
+VS/2
+VS/2
65
70
µs
µs
V
V
5.5 V
78
mA
µA
NOTES
1For information on operation below 250 MHz, see Figure 4.
2See LO Drive section for more details on input matching.
Specifications subject to change without notice.
–2–
REV. 0
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