K6R1004C1D View Datasheet(PDF) - Samsung
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K6R1004C1D Datasheet PDF : 9 Pages
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K6R1004C1D
PRELIMINARY
PRELPIrMeliImNAinRarYy
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
OE
CS
WE
Data in
Data out
tWC
tAW
tCW(3)
tWR(5)
tAS(4)
High-Z
tOHZ(6)
tWP(2)
tDW
tDH
Valid Data
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
WE
Data in
Data out
tAS(4)
High-Z
tWC
tAW
tCW(3)
tWP1(2)
tWR(5)
tWHZ(6)
tDW
tDH
Valid Data
High-Z(8)
tOW
(10)
(9)
-7-
Revision 0.2
December 2001
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