ISL8002 View Datasheet(PDF) - Intersil

Part Name

Description

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ISL8002

Compact Synchronous Buck Regulators

Intersil 

ISL8002, ISL8002A, ISL80019, ISL80019A

PWM

PFM

PWM

CLOCK

16 CYCLES

PFM CURRENT LIMIT

IL

0

NOMINAL +1.5%

LOAD CURRENT

VOUT

NOMINAL

NOMINAL -1.5%

FIGURE 54. SKIP MODE OPERATION WAVEFORMS

Once the skip mode is entered, the pulse modulation starts being

controlled by the SKIP comparator shown in the “Functional

Block Diagram” on page 5. Each pulse cycle is still synchronized

by the PWM clock. The P-FET is turned on at the clock's rising

edge and turned off when the output is higher than 1.5% of the

nominal regulation or when its current reaches the peak Skip

current limit value. Then the inductor current is discharging to 0A

and stays at zero. The internal clock is disabled. The output

voltage reduces gradually due to the load current discharging the

output capacitor. When the output voltage drops to the nominal

voltage, the P-FET will be turned on again at the rising edge of

the internal clock as it repeats the previous operations.

The regulator resumes normal PWM mode operation when the

output voltage drops 1.5% below the nominal voltage.

Overcurrent Protection

The overcurrent protection is realized by monitoring the CSA

output with the OCP comparator, as shown in the “Functional

Block Diagram” on page 5. The current sensing circuit has a gain

of 300mV/A, from the P-FET current to the CSA output. When the

CSA output reaches a threshold, the OCP comparator is tripped to

turn off the P-FET immediately. The overcurrent function protects

the switching converter from a shorted output by monitoring the

current flowing through the upper MOSFET.

Upon detection of overcurrent condition, the upper MOSFET will

be immediately turned off and will not be turned on again until

the next switching cycle. If the overcurrent condition goes away,

the output will resume back into regulation point after the hiccup

mode expires.

Short-Circuit Protection

The short-circuit protection (SCP) comparator monitors the VFB

pin voltage for output short-circuit protection. When the VFB is

lower than 0.3V, the SCP comparator forces the PWM oscillator

frequency to drop to 1/3 of the normal operation value. This

comparator is effective during start-up or an output short-circuit

event.

Negative Current Protection

Similar to the overcurrent, the negative current protection is

realized by monitoring the current across the low-side N-FET, as

shown in the “Functional Block Diagram” on page 5. When the

valley point of the inductor current reaches -1.5A for 2 consecutive

cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the

N-FET will activate discharging the output into regulation. The

control will begin to switch when output is within regulation. The

regulator will be in PFM for 20µs before switching to PWM if

necessary.

PG

PG is an output of a window comparator that continuously monitors

the buck regulator output voltage. PG is actively held low when EN is

low and during the buck regulator soft-start period. After 1ms delay

of the soft-start period, PG becomes high impedance as long as the

output voltage is within nominal regulation voltage set by VFB.

When VFB drops 15% below or raises 15% above the nominal

regulation voltage, the device pulls PG low. Any fault condition forces

PG low until the fault condition is cleared by attempts to soft-start.

There is an internal 5MΩ pull-up resistor to fit most applications. An

external resistor can be added from PG to VIN for more pull-up

strength.

UVLO

When the input voltage is below the undervoltage lock-out (UVLO)

threshold, the regulator is disabled.

Enable, Disable, and Soft Start-Up

After the VIN pin exceeds its rising POR trip point (nominal 2.7V),

the device begins operation. If the EN pin is held low externally,

nothing happens until this pin is released. Once the EN is

released and above the logic threshold, the internal default

soft-start time is 1ms.

Discharge Mode (Soft-Stop)

When a transition to shutdown mode occurs or the VIN UVLO is set,

the outputs discharge to GND through an internal 100Ω switch.

100% Duty Cycle (1MHz Version)

The device features 100% duty cycle operation to maximize the

battery life. When the battery voltage drops to a level that the

device can no longer maintain the regulation at the output, the

regulator completely turns on the P-FET. The maximum dropout

voltage under the 100% duty-cycle operation is the product of the

load current and the ON-resistance of the P-FET.

18

FN7888.2

July 30, 2013

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