IPSH4N03LAG(2008) View Datasheet(PDF) - Infineon Technologies
Part Name
Description
View to exact match
IPSH4N03LAG Datasheet PDF : 10 Pages
| |||
Parameter
Symbol Conditions
IPDH4N03LA G IPSH4N03LA G
min.
Values
typ.
Unit
max.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics6)
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Gate charge total
Gate plateau voltage
Gate charge total, sync. FET
Output charge
C iss
-
C oss
V GS=0 V, V DS=15 V,
f =1 MHz
-
Crss
-
t d(on)
-
tr
V DD=15 V, V GS=10 V,
-
t d(off)
I D=25 A, R G=2.7 Ω
-
tf
-
2400
920
110
9
7
29
4.6
3200 pF
1200
160
14 ns
11
44
7
Q gs
-
8
11 nC
Q g(th)
-
3.9
5.1
Q gd
V DD=15 V, I D=45 A,
-
5.6
8
Q sw
V GS=0 to 5 V
-
10
14
Qg
-
19
26
V plateau
-
3.4
-V
Q g(sync)
V DS=0.1 V,
V GS=0 to 5 V
-
17
23 nC
Q oss
V DD=15 V, V GS=0 V
-
20
27
Reverse Diode
Diode continous forward current
Diode pulse current
Diode forward voltage
Reverse recovery charge
IS
I S,pulse
T C=25 °C
V SD
V GS=0 V, I F=78 A,
T j=25 °C
Q rr
V R=15 V, I F=I S,
di F/dt =400 A/µs
-
-
78 A
-
-
360
-
0.93
1.2 V
-
-
15 nC
6) See figure 16 for gate charge parameter definition
Rev. 1.4
page 3
2008-04-14
Share Link: 