IDT72V845 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

1

tENS

tENH

tCLKH

2

tCLK

tCLKL

REN

NO OPERATION

tREF

tREF

EF

Q0 - Q17

OE

WCLK

tOLZ

tA

tOE

tSKEW1(1)

LAST WORD

tOHZ

WEN

tENS

tDS

tENH

tDH

D0 - D17

FIRST WORD

4295 drw 26

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising

edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.

2. LD = HIGH

3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)

WCLK

WEN

- D0 D17

RCLK

tENS

tDS

W1

tENH

tDH

W2

tSKEW1 (1)

1

W3

2

tDS

W4

W[n +2]

3

W[n+3]

REN

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

tREF

W1

tREF

OR

4295 drw 27

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the

rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH, OE = LOW

3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.

Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)

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