IDT72V845 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

WCLK

D0 - D17

FF

NO WRITE

t

(1)

SKEW1

t DS

t WFF

DATA WRITE

t WFF

WEN

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NO WRITE

t SKEW1(1)

t WFF

t DS

DATA

WRITE

RCLK

t ENS

t ENH

t ENS

t ENH

REN

OE LOW

tA

tA

Q0 - Q17 DATA IN OUTPUT REGISTER

DATA READ

NEXT DATA READ

4295 drw 09

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.

Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)

WCLK

tDS

D0 - D17

tENS

WEN

RCLK

EF

DATA WRITE 1

tENH

tSKEW1

(1)

tFRL

tREF

tDS

tENS

DATA WRITE 2

tENH

tSKEW1

tFRL (1)

tREF

tREF

REN

OE LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

DATA READ

4295 drw 10

NOTES:

1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The

Latency Timing apply only at the Empty Boundary (EF = LOW).

2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.

Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)

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