IDT72801L10 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT72801L10

DUAL CMOS SyncFIFO™ DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9

Integrated Device Technology 

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TWO PRIORITY DATA BUFFER

CONFIGURATION

The two FIFOs contained in the IDT72801/72811/72821/72831/72841/

72851 can be used to prioritize two different types of data shared on a system bus.

When writing from the bus to the FIFO, control logic sorts the intermixed data

according to type, sending one kind to FIFO A and the other kind to FIFO B. Then,

at the outputs, each data type is transferred to its appropriate destination. Additional

IDT72801/72811/72821/72831/72841/72851s permit more than two priority

levels. Priority buffering is particularly useful in network applications.

Processor

Clock

Address

Control

Data

RAM

RAM ARRAY A

RCLKA

Image Processing

Card

Clock

WCLKA OEA

WENA1 RENA

9

DA0-DA8

9

QA0-QA8

VCC

WENA2 RENA2

IDT

72801

72811

72821

72831

72841

72851

Data

Address

Control

Voice Processing

Card

9

RAM ARRAY B

WCLKB RCLKB

Clock

WENB1 OEB2

9

RENB1

Address

Control

DB0-DB8 QB0-QB8

Data

9

WENB2 RENB2

9

VCC

Figure 16. Block Diagram of Two Priority Configuration

I/O Data

I/O Data

3034 drw 17

BIDIRECTIONAL CONFIGURATION

The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can

be used to buffer data flow in two directions. In the example that follows, a

processor can write data to a peripheral controller via FIFO A, and, in turn,

the peripheral controller can write the processor via FIFO B.

Processor

Clock

Address

Control

Data

9

RAM

9

RAM ARRAY A

VCC

WENA2 RENA2

RCLKA

WCLKA OEA

WENA1

RENA1

9

DA0-DA8

QA0-QA8

9

IDT

72801

72811

72821

72831

72841

72851

RAM ARRAY B

RCLKB WENB1

RENB1

OEB WCLKB

QB0-QB8

9

DB0-DB8

RENB2 WENB2

9

Peripheral

Controller

DMA Clock

Address

Control

Data

9

I/O Data

3034 drw 18

Figure 17. Block Diagram of Bidirectional Configuration

15

MARCH 2013

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