IDT72805LB(1996) View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

WCLK

tCLKH

WEN

PAE

RCLK

REN

tENS

tCLKL

tENH

COMMERCIAL TEMPERATURE RANGE

tPAE

n + 1 words

in FIFO

tPAE

tENS

n words in FIFO

3139 drw 12

NOTE:

1. PAE is offset = n. Number of data words written into FIFO already = n.

Figure 12. Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

(1)

tENS

tENH

WEN

PAF

RCLK

REN

tPAF

Full – m words

in FIFO(2)

tPAF

tENS

Full – (m + 1) words

in FIFO(3)

3139 drw 13

NOTES:

1. PAF offset = m. Number of data words written into FIFO already = 256 - (m + 1) for the IDT72805LB, 512 - (m + 1) for the IDT72815LB, 1024 - (m + 1)

for the IDT72825LB.

2. 256 - m words in IDT72805LB, 512 - m words in IDT72815LB, 1024 - m words in IDT72825LB.

3. 256 - (m + 1) words in IDT72805LB, 512 - (m + 1) words in IDT72815LB, 1024 - (m + 1) words in IDT72825LB.

Figure 13. Programmable Almost-Full Flag Timing

5.17

15

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