IDT72801 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT72801

DUAL CMOS SyncFIFO™

Integrated Device Technology 

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™

256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Commercial

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Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fS

Clock Cycle Frequency

— 83.3 — 66.7 — 50

— 40

— 28.6 MHz

tA

Data Access Time

28

2 10

2 12

3 15

3 20 ns

tCLK Clock Cycle Time

12 —

15 —

20 —

25 —

35 — ns

tCLKH Clock High Time

5—

6—

8—

10 —

14 — ns

tCLKL Clock Low Time

5—

6—

8—

10 —

14 — ns

tDS Data Set-up Time

3—

4—

5—

6—

8 — ns

tDH Data Hold Time

0—

1—

1—

1—

2 — ns

tENS Enable Set-up Time

3—

4—

5—

6—

8 — ns

tENH

tRS

Enable Hold Time

Reset Pulse Width(1)

0—

12 —

1—

15 —

1—

20 —

1—

25 —

2 — ns

35 — ns

tRSS Reset Set-up Time

12 —

15 —

20 —

25 —

35 — ns

tRSR Reset Recovery Time

12 —

15 —

20 —

25 —

35 — ns

tRSF Reset to Flag Time and Output Time

— 12

— 15

— 20

— 25

— 35 ns

tOLZ Output Enable to Output in Low-Z(2)

0—

0—

0—

0—

0 — ns

tOE Output Enable to Output Valid

37

38

3 10

3 13

3 15 ns

tOHZ Output Enable to Output in High-Z(2)

37

38

3 10

3 13

3 15 ns

tWFF Write Clock to Full Flag

—8

— 10

— 12

— 15

— 20 ns

tREF Read Clock to Empty Flag

—8

— 10

— 12

— 15

— 20 ns

tPAF Write Clock to Programmable

Almost-Full Flag

—8

— 10

— 12

— 15

— 20 ns

tPAE Read Clock to Programmable

Almost-Empty Flag

—8

— 10

— 12

— 15

— 20 ns

tSKEW1 Skew Time Between Read

Clock and Write Clock

for Empty Flag and Full Flag

5—

6—

8—

10 —

12 — ns

tSKEW2 Skew Time Between Read Clock

and Write Clock for Programmable

Almost-Empty Flag and

Programmable Almost-Full Flag

22 —

28 —

35 —

40 —

42 — ns

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

3034 tbl 07

5V

1.1K

AC TEST CONDITIONS

In Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns

1.5V

1.5V

See Figure 1

3034 tbl 08

D.U.T.

680Ω

30pF*

3034 drw 03

or equivalent circuit

Figure 1. Output Load

*Includes jig and scope capacitances.

5.15

5

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