72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
RCLKA (RCLKB)
tCLKH
tCLK
tCLKL
RENA1, RENA2
(RENB1, RENB2)
tENS
tENH
NO OPERATION
EFA (EFB)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
tREF
tA
tOLZ
tOE
VALID DATA
tOHZ
WCLKA, WCLKB
tSKEW1(1)
tREF
COMMERCIAL TEMPERATURE
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change
state until the next RCLKA (RCLKB) edge.
Figure 6. Read Cycle Timing
5.15
11