IDT723611 View Datasheet(PDF) - Integrated Device Technology

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IDT723611

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

COMMERCIAL TEMPERATURE RANGES

The setup and hold-time constraints to the port clocks for

the port chip selects (CSA, CSB) and write/read selects (W/

RA, W/RB) are only for enabling write and read operations and

are not related to HIGH-impedance control of the data out-

puts. If a port enable is LOW during a clock cycle, the port’s

chip select and write/read select can change states during the

setup and hold-time window of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO flag is synchronized to its port clock through two

flip-flop stages. This is done to improve the flags’ reliability by

reducing the probability of mestastable events on their outputs

when CLKA and CLKB operate asynchronously to one an-

other. FF and AF are synchronized to CLKA. EF and AE are

synchronized to CLKB. Table 4 shows the relationship to the

flags to the FIFO.

EMPTY FLAG (EF)

The FIFO empty flag is synchronized to the port clock that

reads data from its array (CLKB). When the empty flag is

HIGH, new data can be read to the FIFO output register.

When the empty flag is LOW, the FIFO is empty and attempted

FIFO reads are ignored.

The FIFO read pointer is incremented each time a new

word is clocked to its output register. The state machine that

controls an empty flag monitors a write pointer and read

pointer comparator that indicates when the FIFO SRAM

status is empty, empty+1, or empty+2. A word written to the

FIFO can be read to the FIFO output register in a minimum of

three port-B clock (CLKB) cycles. Therefore, an empty flag is

LOW if a word in memory is the next data to be sent to the FIFO

output register and two CLKB cycles have not elapsed since

the time the word was written. The empty flag of the FIFO is

set HIGH by the second LOW-to-HIGH transition of CLKB,

and the new data word can be read to the FIFO output register

in the following cycle.

A LOW-to-HIGH transition on CLKB begins the first syn-

chronized cycle of a write if the clock transition occurs at time

tSKEW1 or greater after the write. Otherwise, the subsequent

Number of Words

in the FIFO

0

1 to X

(X+1) to [64-(X+1)]

(64-X) to 63

64

Synchronized

to CLKB

EF AE

L

L

H

L

H

H

H

H

H

H

Synchronized

to CLKA

AF FF

H

H

H

H

H

H

L

H

L

L

Table 4. FIFO Flag Operation

Note:

X is the value in the almost-empty flag and almost-full

flag register.

CLKB cycle can be the first synchronization cycle (see figure

4).

FULL FLAG (FF)

The FIFO full flag is synchronized to the port clock that

writes data to its array (CLKA). When the full flag is HIGH, an

SRAM location is free to receive new data. No memory

locations are free when the full flag is LOW and attempted

writes to the FIFO are ignored.

Each time a word is written to the FIFO, its write pointer is

incremented. The state machine that controls the full flag

monitors a write pointer and read pointer comparator that

indicates when the FIFO SRAM status is full, full-1, or full-2.

From the time a word is read from the FIFO, its previous

memory location is ready to be written in a minimum of three

port-A clock cycles. Therefore, a full flag is LOW if less than

two CLKA cycles have elapsed since the next memory write

location has been read. The second LOW-to-HIGH transition

on CLKA after the read sets the full flag HIGH and data can be

written in the following clock cycle.

A LOW-to-HIGH transition on CLKA begins the first syn-

chronization cycle of a read if the clock transition occurs at

time tSKEW1 or greater after the read. Otherwise, the subse-

quent clock cycle can be the first synchronization cycle (see

figure 5).

ALMOST-EMPTY FLAG (AE)

The FIFO almost empty-flag is synchronized to the port

clock that reads data from its array (CLKB). The state

machine that controls the almost-empty flag monitors a write

pointer and read pointer comparator that indicates when the

FIFO SRAM status is almost empty, almost empty+1, or

almost empty+2. The almost-empty state is defined by the

value of the almost-full and almost-empty offset register (X).

This register is loaded with one of four preset values during a

device reset (see reset above). The almost-empty flag is LOW

when the FIFO contains X or less words in memory and is

HIGH when the FIFO contains (X+1) or more words.

Two LOW-to-HIGH transitions on the port-B clock (CLKB)

are required after a FIFO write for the almost-empty flag to

reflect the new level of fill. Therefore, the almost-empty flag

of a FIFO containing (X+1) or more words remains LOW if two

CLKB cycles have not elapsed since the write that filled the

memory to the (X+1) level. The almost-empty flag is set HIGH

by the second CLKB LOW-to-HIGH transition after the FIFO

write that fills memory to the (X+1) level. A LOW-to-HIGH

transition on CLKB begins the first synchronization cycle if it

occurs at time tSKEW2 or greater after the write that fills the

FIFO to (X+1) words. Otherwise, the subsequent CLKB cycle

can be the first synchronization cycle (see figure 6).

ALMOST FULL FLAG (AF)

The FIFO almost-full flag is synchronized to the port clock

that writes data to its array (CLKA). The state machine that

controls an almost-full flag monitors a write pointer and read

pointer comparator that indicates when the FIFO SRAM

status is almost full, almost full-1, or almost full-2. The almost-

full state is defined by the value of the almost-full and almost-

10

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