IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE,
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after RT is setup, the PAE flag will be updated. HF is asynchronous, thus
the rising edge of RCLK that RT is setup will update HF. PAF is synchro-
nized to WCLK, thus the second rising edge of WCLK that occurs tSKEW
after the rising edge of RCLK that RT is setup will update PAF. RT is
synchronized to RCLK.
11
OCTOBER 17, 2005