A42L0616 View Datasheet(PDF) - AMIC Technology
Part Name
Description
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A42L0616 Datasheet PDF : 25 Pages
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Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
A42L0616 Series
-45
-50
-60
Unit
45
50
60
ns
23
25
30
ns
13
15
17
ns
13
13
15
ns
79
84
104
ns
16
20
25
ns
Functional Description
The A42L0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column
address. RAS and CAS are used to strobe the row
address and the column address, respectively.
The A42L0616 has two CAS inputs: LCAS controls I/O0-
I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using LCAS
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS/CAS operation. A Write cycle is executed by
holding the WE signal low during RAS/CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS, CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving
shorter cycle times.
The A42L0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (tcp). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 1024(1K)
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle (RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh
counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization
cycles containing a RAS clock. During Power-On, the
VCC current is dependent on the input levels of RAS and
CAS . It is recommended that RAS and CAS track with
VCC or be held at a valid VIH during Power-On to avoid
current surges.
PRELIMINARY (June, 2001, Version 0.0)
2
AMIC Technology, Inc.
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