IDT7024 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
View to exact match
IDT7024 Datasheet PDF : 22 Pages
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IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)(M/S = VIH)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
VALID
2740 drw 13
Timing Waveform of Write with BUSY
tWP
R/W"A"
BUSY"B"
tWB(3)
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
tWH(1)
,
2740 drw 14
61.442
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