IDT7008L(2018) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
View to exact match
IDT7008L Datasheet PDF : 20 Pages
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IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7008X15
Com'l Only
7008X20
Com'l & Ind
7008X25
Com'l Only
7008X35
Com'l Only
7008X55
Com'l & Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
35
____
55
____
ns
tAA
Address Access Time
____
15
____
20
____
25
____
35
____
55 ns
tACE
Chip Enable Access Time(4)
____
15
____
20
____
25
____
35
____
55 ns
tAOE
Output Enable Access Time
____
10
____
12
____
13
____
20
____
30 ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
3
____
3
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
____
15
____
25 ns
tPU
Chip Enable to Power Up Time(2)
0
____
0
____
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(2)
____
15
____
20
____
25
____
35
____
50 ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
12
____
15
____
15
____
ns
tSAA
Semaphore Address Access Time
____
15
____
20
____
25
____
35
____
55 ns
3198 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(6)
7008X15
Com'l Only
7008X20
Com'l & Ind
7008X25
Com'l Only
7008X35
Com'l Only
7008X55
Com'l & Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
15
____
20
____
25
____
35
____
55
____
ns
tEW
Chip Enable to End-of-Write(3)
12
____
15
____
20
____
30
____
45
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
20
____
30
____
45
____
ns
tAS
Address Set-up Time(3)
0
____
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
15
____
20
____
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
15
____
15
____
30
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
____
15
____
25
ns
tDH
Data Hold Time(5)
0
____
0
____
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
____
10
____
12
____
15
____
15
____
25
ns
tOW
Output Active from End-of-Write(1,2,5)
0
____
0
____
0
____
0
____
0
____
ns
tSWRD SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
5
____
5
____
ns
NOTES:
3198 tbl 13
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
5. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
6. 'X' in part numbers indicates power rating (s or L).
6.942
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