MH32DS64APFH-6L View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
View to exact match
MH32DS64APFH-6L Datasheet PDF : 52 Pages
| |||
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S64APFH-6,-6L,-7,-7L
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
0 Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9 SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-6,-6L
-7,-7L
10
SDRAM Access from Clock
-6,-6L
tAC for CL=3
-7,-7L
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
SPD enrty data
128
256 Bytes
SDRAM
A0-A12
A0-A9
2BANK
x64
0
LVTTL
7.5ns
10ns
5.4ns
6ns
Non-PARITY
self refresh(7.8uS)
x8
N/A
1
1/2/4/8/Full page
4bank
2/3
19
CS# Latency
20
Write Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
0
0
non-buffered,non-registered
Precharge All,Auto precharge
10ns
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
26 SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
28
Row Active to Row Active Min.
29
RAS to CAS Delay Min
30
Active to Precharge Min
-6,-6L
-7,-7L
-7,-7L
-6,-6L
-7,-7L
6ns
N/A
N/A
20ns
15ns
20ns
20ns
45ns
50ns
SPD DATA(hex)
80
08
04
0D
0A
02
40
00
01
75
A0
54
60
00
82
08
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
0F
14
14
2D
32
MIT-DS-0392-0.1
MITSUBISHI
ELECTRIC
( 4 / 52 )
16.Apr.2000
Share Link: 