HY57V641620ELT View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

View to exact match

HY57V641620ELT

4Bank x 1M x 16bits Synchronous DRAM

Hynix Semiconductor 

Synchronous DRAM Memory 64Mbit (4Mx16bit)

HY57V641620E(L/S)T(P) Series

PIN DESCRIPTION

SYMBOL

CLK

CKE

CS

BA0, BA1

A0 ~ A11

RAS, CAS, WE

UDQM, LDQM

DQ0 ~ DQ15

VDD / VSS

VDDQ / VSSQ

NC

TYPE

DESCRIPTION

Clock

The system clock input. All other inputs are registered to the

SDRAM on the rising edge of CLK

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will

be one of the states among power down, suspend or self refresh

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Bank Address

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

Address

Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7

Auto-precharge flag: A10

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write

mode

Data Input / Output Multiplexed data input / output pin

Power Supply / Ground Power supply for internal circuits and input buffers

Data Output Power /

Ground

Power supply for output buffers

No Connection

No connection

Rev. 1.5 / Feb. 2005

4

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