HEF4035B View Datasheet(PDF) - Philips Electronics
Part Name
Description
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HEF4035B Datasheet PDF : 8 Pages
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Philips Semiconductors
4-bit universal shift register
Product speciļ¬cation
HEF4035B
MSI
DESCRIPTION
The HEF4035B is a fully synchronous edge-triggered 4-bit
shift register with a clock input (CP), four synchronous
parallel data inputs (P0 to P3), two synchronous serial data
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O0 to O3),
a true/complement input (T/C) and an overriding
asynchronous master reset input (MR). Each register is of
a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP
input. When PE is HIGH, data is loaded into the register
from P0 to P3 on the LOW to HIGH transition of CP.
When PE is LOW, data is shifted into the first register
position from J and K and all the data in the register is
shifted one position to the right on the LOW to HIGH
transition of CP. D-type entry is obtained by
interconnecting J and K. When J = HIGH and K = LOW the
first stage is in the toggle mode. When J = LOW and
K = HIGH the first stage is in the hold mode.
The outputs (O0 to O3) are either inverting or non-inverting,
depending on T/C state. With T/C HIGH, O0 to O3 are
non-inverting (active HIGH) and when T/C is LOW, O0 to
O3 are inverting (active LOW).
A HIGH on MR resets all four bit positions (O0 to
O3 = LOW if T/C = HIGH, O0 to O3 = HIGH if T/C = LOW)
independent of all other input conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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