HEF4015BU View Datasheet(PDF) - Philips Electronics
Part Name
Description
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HEF4015BU Datasheet PDF : 5 Pages
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Philips Semiconductors
Dual 4-bit static shift register
Product specification
HEF4015B
MSI
DESCRIPTION
The HEF4015B is a dual edge-triggered 4-bit static shift
register (serial-to-parallel converter). Each shift register
has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (O0 to O3) and an overriding
asynchronous master reset input (MR). Information
present on D is shifted to the first register position, and all
the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of CP. A HIGH on MR
clears the register and forces O0 to O3 to LOW,
independent of CP and D. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4015BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4015BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4015BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
DA, DB
MRA, MRB
CPA, CPB
O0A, O1A, O2A, O3A
O0B, O1B, O2B, O3B
serial data input
master reset input (active HIGH)
clock input (LOW-to-HIGH
edge-triggered)
parallel outputs
parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4015B are:
• Serial-to-parallel converter
• Buffer stores
• General purpose register
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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