HCC4094B View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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HCC4094B

8–STAGE SHIFT-AND-STORE BUS REGISTER

STMicroelectronics 

HCC/HCF4094B

8–STAGE SHIFT-AND-STORE BUS REGISTER

. 3-STATE PARALLEL OUTPUTS FOR CON-

NECTION TO COMMON BUS

. SEPARATE SERIAL OUTPUTS SYN-

CHRONOUS TO BOTH POSITIVE AND NEGA-

TIVE CLOCK EDGES FOR CASCADING

. MEDIUM SPEED OPERATION 5MHz AT 10V

. STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

. QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

. 5V, 10V, AND 15V PARAMETRIC RATINGS

. INPUT CURRENT OF 100nA AT 18V AND 25°C

FOR HCC DEVICE

. 100% TESTED FOR QUIESCENT CURRENT

. MEETS ALL REQUIREMENTS OF JEDECTEN-

TATIVE STANDARD N°. 13A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”

EY

(Plastic Package)

F

(Ceramic Frit Seal Package)

M1

(Micro Package)

C1

(Plastic Chip Carrier)

ORDER CODES :

HCC4094BF HCF4094BM1

HCF4094BEY HCF4094BC1

DESCRIPTION

The HCC4094B (extended temperature range) and

HCF4094B (intermediate temperature range) are

monolithic integrated circuits available in 16-lead

dual in-line plastic or ceramic packageand plastic

micropackage.

The HCC/HCF4094B is an 8-stage serial shift reg-

ister having a storage latch associated with each

stage for strobing data from the serial input to par-

allel buffered 3-state outputs. The parallel outputs

may be connected directly to common bus lines.

Data is shifted on positive clock transitions. The data

in each shift register stage is transferred to the stor-

age register when the STROBE input is high. Data

in the storage register appears at the outputs when-

ever the OUTPUT-ENABLE signal is high. Two ser-

ial outputs are available for cascading a number of

HCC/HCF4094B devices. Data is available at the

QS serial output terminal on positive clock edges to

allow for high-speed operation in cascaded systems

in which the clock rise time is fast. The same serial

information, available at the Q’S terminal on the next

negative clock edge, provides a means for cascad-

ing HCC/HCF4094B devices when the clock rise

time is slow.

June 1989

PIN CONNECTIONS

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