HEC40192BT View Datasheet(PDF) - Philips Electronics
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Description
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HEC40192BT Datasheet PDF : 9 Pages
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Philips Semiconductors
4-bit up/down decade counter
Product specification
HEF40192B
MSI
DESCRIPTION
The HEF40192B is a 4-bit synchronous up/down decade
counter. The counter has a count-up clock input (CPU), a
count-down clock input (CPD), an asynchronous parallel
load input (PL), four parallel data inputs (P0 to P3), an
asynchronous master reset input (MR), four counter
outputs (O0 to O3), an active LOW terminal count-up
(carry) output (TCU) and an active LOW terminal
count-down (borrow) output (TCD).
The counter outputs change state on the LOW to HIGH
transition of either clock input. However, for correct
counting, both clock inputs cannot be LOW
simultaneously. The outputs TCU and TCD are normally
HIGH. When the circuit has reached the maximum count
state of ‘9’, the next HIGH to LOW transition of CPU will
cause TCU to go LOW. TCU will stay LOW until CPU goes
HIGH again. Likewise, output TCD will go LOW when the
circuit is in the zero state and CPD goes LOW. When PL is
LOW, the information on P0 to P3 is asynchronously
loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter
stages are of a static toggle type flip-flop.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
PINNING
PL
P0 to P3
CPU
CPD
MR
TCU
TCD
O0 to O3
parallel load input (active LOW)
parallel data inputs
count-up clock pulse input (LOW to HIGH,
edge-triggered)
count-down clock pulse input (LOW to
HIGH, edge-triggered)
master reset input (asynchronous)
buffered terminal count-up (carry) output
(active LOW)
buffered terminal count-down
(borrow) output (active LOW)
buffered counter outputs
HEF40192BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40192BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40192BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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