FSL137MRIN View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

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FSL137MRIN

Green-Mode Fairchild Power Switch (FPS™)

Fairchild Semiconductor 

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (CVCC) connected to the VCC pin, as

illustrated in Figure 19. When VCC reaches 12 V, the

FSL137MRIN begins switching and the internal high-

voltage current source is disabled. Normal switching

operation continues and the power is supplied from the

auxiliary transformer winding unless VCC goes below the

stop voltage of 7.5 V.

VDC

CVCC

VCC

2

VSTR

5

ICH

7.5V/12.0V

VCC Good

VREF

Internal

Bias

Figure 19. Startup Block

2. Soft-Start: The internal soft-start circuit increases

PWM comparator inverting input voltage, together with

the SenseFET current, slowly after startup. The typical

soft-start time is 15 ms. The pulse width to the power

switching device is progressively increased to establish

the correct working conditions for the transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased to smoothly

establish the required output voltage. This helps prevent

transformer saturation and reduces stress on the

secondary diode during startup.

3. Feedback Control: This device employs Current-

Mode control, as shown in Figure 20. An opto-coupler

(such as the FOD817) and shunt regulator (such as the

KA431) are typically used to implement the feedback

network. Comparing the feedback voltage with the

voltage across the RSENSE resistor makes it possible to

control the switching duty cycle. When the reference pin

voltage of the shunt regulator exceeds the internal

reference voltage of 2.5 V, the opto-coupler LED current

increases, pulling down the feedback voltage and

reducing drain current. This typically occurs when the

input voltage is increased or the output load is decreased.

3.1 Pulse-by-Pulse Current Limit: Because Current-

Mode control is employed, the peak current through

the SenseFET is limited by the inverting input of PWM

comparator (VFB*), as shown in Figure 20. Assuming

that the 90 μA current source flows only through the

internal resistor (3R + R =25 kΩ), the cathode voltage

of diode D2 is about 2.8 V. Since D1 is blocked when

the feedback voltage (VFB) exceeds 2.84 V, the

maximum voltage of the cathode of D2 is clamped at

this voltage. Therefore, the peak value of the current

through the SenseFET is limited.

3.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the RSENSE

resistor leads to incorrect feedback operation in

Current-Mode PWM control. To counter this effect, the

LEB circuit inhibits the PWM comparator for tLEB

(300 ns) after the SenseFET is turned on.

VOUT

VFB

FOD817

FB

3

CFB

VCC

VREF

IDELAY

D1

IFB

3R

D2

VFB* R

OSC

PWM

Gate

Driver

LEB(300ns)

Drain

6,7,8

KA431

VOSP

VSD

OSP

AOCP

OLP

RSENSE

VAOCP

GND

1

Figure 20. Pulse Width Modulation Circuit

© 2012 Fairchild Semiconductor Corporation

FSL137MRIN • Rev. 1.0.1

10

www.fairchildsemi.com

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