AM29DL400B View Datasheet(PDF) - Advanced Micro Devices

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AM29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

Advanced Micro Devices 

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is a latch used to store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. Table 1 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29DL400B Device Bus Operations

DQ8–DQ15

Read

Write

Operation

Standby

CE# OE# WE# RESET#

L

LH

H

L HL

H

VCC ±

0.3 V

X

X

VCC ±

0.3 V

Addresses

(Note 1)

AIN

AIN

X

DQ0–

DQ7

DOUT

DIN

BYTE#

= VIH

DOUT

DIN

BYTE#

= VIL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z High-Z

High-Z

Output Disable

L HH

H

X

High-Z High-Z

High-Z

Reset

X XX

L

X

High-Z High-Z

High-Z

Sector Address,

Sector Protect (Note 2)

L HL

VID

A6 = L, A1 = H, DIN

X

X

A0 = L

Sector Address,

Sector Unprotect (Note 2)

L HL

VID

A6 = H, A1 = H, DIN

X

X

A0 = L

Temporary Sector Unprotect

X XX

VID

AIN

DIN

DIN

High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0-15 are active and controlled by CE#

and OE# .

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at VIH. The BYTE# pin determines whether the

device outputs array data in words or bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. Each bank

remains enabled for read access until the command

register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing spec-

ifications and to Figure 13 for the timing diagram. ICC1

in the DC Characteristics table represents the active

current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

8

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