74194 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

View to exact match

74194

4 BIT PIPO SHIFT REGISTER

STMicroelectronics 

M54HC194

M74HC194

. HIGH SPEED

tPD = 12 ns (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 4 µA (MAX.) AT TA = 25 °C

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS194

4 BIT PIPO SHIFT REGISTER

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M 54HC 19 4F 1R

M 74H C1 94 M1 R

M 74HC 19 4B 1R

M 74H C1 94 C1 R

DESCRIPTION

The M54/74HC194 is a high speed CMOS 4 BIT PIPO

SHIFT REGISTER fabricated in silicon gate C2MOS

technology. It has the same high speed performance

of LSTTL combined with true CMOS low power con-

sumption. This SHIFT REGISTER is designed to in-

corporate virtually all of the features a system designer

may want in a shift register. It features parallel inputs,

parallel outputs, right shift and left shift serial inputs,

clear line. The register has four distinct modes of oper-

ation : PARALLEL (broadside) LOAD ; SHIFT RIGHT

(in the direction QA QD); SHIFT LEFT ; INHIBIT

CLOCK (do nothing). Synchronous parallel loading is

accomplished by applying the four data bits and taking

both mode control inputs, S0 and S1 high. The data

are loaded into their respective flip-flops and appear

at the outputs after the positive transition of the

CLOCK input. During loading, serial data flow is in-

hibited. Shift right is accomplished synchronously with

the rising edge of the clock pulse when S0 is high and

S1 is low. Serial data for this mode is entered at the

SHIFT RIGHT data input. When S0 is low and S1 is

high,data shifts left synchronously and new data is en-

tered at the SHIFT LEFT serial input. Clocking of the

flipflops is inhibited when both mode control inputs are

low. The mode control inputs should be changed only

when the CLOCK input is high. All inputs are equipped

with protection circuits against static discharge and

transient excess voltage.

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

October 1992

1/12

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