ETC5067N(1994) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ETC5067N
(Rev.:1994)

POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTER WITH RECEIVE

STMicroelectronics 

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

pulses are being used. For 64 kHz operation, the

frame sync pulses must be kept low for a minimum

of 160 ns (see Fig 1). The DX TRI-STATE output

buffer is enabled with the rising edge of FSX or the

rising edge of BCLKX, whichever comes later, and

the first bit clocked out is the sign bit. The following

seven BCLKX rising edges clock out the remaining

seven bits. The DX output is disabled by the falling

BCLKX edge following the eighth rising edge, or by

FSX going low, whichever comes later. A rising edge

on the receive frame sync pulse, FSR, will cause the

PCM data at DR to be latched in on the next eight

falling edges of BCLKR (BCLKx in synchronous

mode). Both devices may utilize the long frame sync

pulse in synchronous or asynchronous mode.

TRANSMIT SECTION

The transmit section input is an operational amplifier

with provision for gain adjustmentusing two external

resistors, see figure 4. The low noiseand wide band-

width allow gains in excess of 20 dB across the

audio passband to be realized. The op amp drives

a unity gain filter consisting of RC active pre-filter,

followed by an eighth order switched-capacitor

bandpass filter directly drives the encoder sample-

and-hold circuit. The A/D is of companding type ac-

cording to A-law (ETC5067 and ETC5067-X) or µ-

law (ETC5064 and ETC5064-X) coding conven-

tions. A precision voltage reference is trimmed in

manufacturing to provide an input over load (tMAX)

of nominally 2.5V peak (see table of Transmission

Characteristics). The FSX frame sync pulse controls

the sampling of the filer output,and then the succes-

sive-approximationencodingcycle begins.The8-bit

code is then loaded into a buffer and shifted out

throughDX at the next FSX pulse. the total encoding

delay will be approximately 165µs (due to the trans-

mit filter) plus 125µs (due to encoding delay), which

totals 290µs. Any offset voltage due to the filters or

comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consist of an expanding DAC

which drives a fifth order switched-capacitor low

pass filter clocked at 256kHz. The decoder is A-law

(ETC5067 and ETC5067-X) or µ–law (ETC5064

and ETC5064-X) and the 5 th order low pass filter

corrects for the sin x/x attenuation due to the 8kHz

sample and hold. The filter is then followed by a 2

nd order RC active post-filter and power amplifier

capable of driving a 600Ω load to a level of 7.2dBm.

The receive section is unity-gain. Upon the oc-

curence of FSR, the data at the DR input is clocked

in on the falling edge of the next eight BCLKR

(BCKLX) periods.At the end ofthe decoder time slot,

the decoding cycle begins, and 10µs later the de-

coder DAC outputis updated.The total decoder de-

lay is about10µs (decoder up-date) plus 110µs (fil-

ter delay) plus 62.5µs (1/2 frame), which gives ap-

proximately 180µs.

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided

for directly driving a matched line interface trans-

former. The gain of the first power amplifier can be

adjusted to boost the ± 2.5V peak output signal from

the receive filter up ± 3.3V peak into an unbalanced

300Ω load, or ±4.0V into an unbalanced15kΩ load.

The second power amplifier is internally connected

in unity-gain inverting mode to give 6dB of signal

gain for balanced loads. Maximum power transfer to

a 600Ω subscriber line termination is obtained by

differientially driving a balanced transformer with a

√2 : 1 turns ratio, as shown in figure 4. A total peak

power of 15.6dBm can be delivered to the load plus

termination. Both power amplifier can be powered

down independentlyfrom the PDN input by connect-

ing the VPI input to VBB saving approximately 12

mW of power.

ABSOLUTE MAXIMUM RATINGS

S ym b o l

VCC

VBB

VIN, VOUT

Toper

Tstg

Parameter

VCC to GNDA

VBB to GNDA

Voltage at any Analog Input or Output

Voltage at any Digital Input or Output

Operating Temperature Range: ETC5064/67

ETC5064-X/67-X

Storage Temperature Range

Lead Temperature (soldering, 10 seconds)

Valu e

7

-7

VCC +0.3 to VBB -0.3

VCC +0.3 to GNDA -0.3

-25 to +125

-40 to +125

-65 to +150

300

Unit

V

V

V

V

°C

°C

°C

°C

5/18

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