EDS1232AATA-60TI View Datasheet(PDF) - Elpida Memory, Inc
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EDS1232AATA-60TI Datasheet PDF : 53 Pages
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EDS1232AATA-TI
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
READ
BST
DQ
(CL = 2)
out
out
out
High-Z
DQ
(CL = 3)
High-Z
out
out
out
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
DQ
WRITE
BST
in
in
in
in
Burst Stop at Write
High-Z
Data Sheet E0305E30 (Ver. 3.0)
31
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