E649APJ View Datasheet(PDF) - Semtech Corporation

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E649APJ

Octal Pin Electronics Driver/Receiver

Semtech Corporation 

Edge649

TEST AND MEASUREMENT PRODUCTS

Application Infor mation

Power Supplies

The Edge649 uses three power supplies: VDD, VCC and

VEE. VDD is the digital supply for all of the data inputs

and outputs. VCC and VEE are the analog power supplies

for the Edge649 drivers and comparators. In order to

protect the Edge649 and avoid damaging it, the following

power supply requirements must be satisifed at all times:

VCC and VEE, which power the DUT drivers and receivers,

should also be decoupled to GND with a .1 µF chip

capacitor in parallel with a .001 µF chip capacitor. A

VCC and VEE plane, or at least a solid power bus, is

recommended for optimal performance.

Also,

VEE ≤ GND ≤ VDD ≤ VCC

VEE ≤ All Inputs ≤ VCC at all times

The three-diode configuration shown in Figure 5, used

on a once-per-board basis, insures power supply

sequence and fault tolerance.

VHIGH and VLOW Decoupling

As the VHIGH and VLOW inputs are unbuffered and must

supply the driver output current, decoupling capacitors

for these inputs are recommended in proportion to the

amount of output current the application requires

VCC

Expanding the Common Mode Range

Although the Edge649 can drive and receive 11V swings,

VDD

these 11 V signals can be adjusted over an 14V range.

1N5820 or

Equivalent

By using programmable regulators V1 and V2 for the

VCC and VEE supplies (feasible because these two

analog power supplies do not supply driver output

current), the Edge649 I/O range can be optimized for a

variety of applications (see Figure 6).

VEE

Figure 5. Power Supply Protection Scheme

The sequence below can be used as a guideline with the

Edge649:

Power-On Sequencing

1. VCC (substrate)

2. VEE

3. VDD

4. Inputs

Power-Off Sequencing

1. Inputs

2. VDD

3. VEE

4. VCC

V1

VCC

Edge 649

VDD

V2

Power Supplies Decoupling

Figure 6.

VDD, which provides the digital power, should be

decoupled to GND with a .1 µF chip capacitor in parallel

with a .001 µF chip capacitor. The bypass capacitors

should be as close to the device as possible. Power and

ground planes are recommended to provide a low

inductance return path.

There are three rules which govern the supplies V1 and

V2:

1) VDD + 1.5V ≤ V1 ≤ +11V

2) –3V ≤ V2 ≤ 0V

3) (V1 – V2) ≤ 11V

Revision 5 / October 21, 2002

6

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