EBD11UD8ABFB View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
View to exact match
EBD11UD8ABFB Datasheet PDF : 19 Pages
| |||
EBD11UD8ABFB
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM banks
0 0 0 0 0 0 1 0 02H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = 2.5
-6B
0 1 1 0 0 0 0 0 60H
-7A, -7B
SDRAM access from clock (tAC)
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
0 1 1 1 0 0 0 0 70H
0 1 1 1 0 1 0 1 75H
DIMM configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
0 0 0 0 0 0 0 1 01H
0 0 0 0 1 1 1 0 0EH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01H
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02H
21
SDRAM module attributes
0 0 1 0 0 0 0 0 20H
22
SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
23
Minimum clock cycle time at CL = 2
-6B, -7A
0
1
1
1
0
1
0
1
75H
-7B
1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
24
clock at CL = 2
0 1 1 1 0 0 0 0 70H
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
25 to 26
0 0 0 0 0 0 0 0 00H
27
Minimum row precharge time (tRP)
-6B
0
1
0
0
1
0
0
0
48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
64
0
SSTL2
6.0ns*1
7.5ns*1
0.7ns*1
0.75ns*1
None.
7.6µs
×8
None.
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
7.5ns*1
10ns*1
0.7ns*1
0.75ns*1
18ns
20ns
Preliminary Data Sheet E0296E20 (Ver. 2.0)
5
Share Link: 